These kinds of architectures are pretty cool to play with but getting good performance out of them comes with an important caveat that is not immediately obvious to many people.
It is not sufficient to recompile your C/C++ code to gain the performance advantages, you have to redesign the data structures in your code to match the characteristics of the hardware. For many code bases, redesigning all of your data structures is tantamount to a rewrite. This is not something a compiler can do for you automagically.
A follow-on caveat is that to design optimal data structures for these types of architectures, you need to be comfortable with understanding how silicon actually works and know how to do microarchitecture specific optimization in high-level code. Someone who has these skills can usually squeeze out several times the performance of typical software code on more vanilla CPUs, which closes the performance gap quite a bit and for some codes the latest greatest Intel CPU will actually be faster than a hybrid architecture.
The thing to keep in mind is that most benchmark comparisons I've seen for these types of architectures are (1) narrowly selected for workloads where they excel and (2) usually compare naively optimized CPU code with expertly optimized coprocessor code. In reality, due to skill availability you often see the reverse with expertly optimized CPU code and naively optimized coprocessor code that virtually erases the apparent performance advantages.
The major hurdle for exotic coprocessor architectures is that expert code designers that know how to exploit and use these architectures are incredibly rare. Consequently, you rarely see what they can actually do. Intel's Xeon Phi coprocessor has had similar issues.
If the story this article tells us is true, the FPGA part(i.e. the "personality ") is optimizied by the guys at convey , which created a variety of profiles for specific application areas - and that supposed to take most of the burden of understanding of an FPGA from the programmer, and he really have to understand a high level view of that "personality".
Of course until actually using such tools, it's hard to tell. But the fact micron, a huge company which most likely is interested in big businesses ackuired convey, is a good sign to the use of such tools for the mass market and not just a bunch of highly trained experts.
Companies like Micron are looking to reduce their exposure to the commodity hardware business by getting more into services. This platform still looks pretty complicated to use, but Micron/Convey would probably be happy to take care of that -- and that's probably where most of the profit is.
Still,can convey be important to the growth/diversification of micron, a ~$35 billion company, without being big and creating at least a medium change in the market ?
It is not sufficient to recompile your C/C++ code to gain the performance advantages, you have to redesign the data structures in your code to match the characteristics of the hardware. For many code bases, redesigning all of your data structures is tantamount to a rewrite. This is not something a compiler can do for you automagically.
A follow-on caveat is that to design optimal data structures for these types of architectures, you need to be comfortable with understanding how silicon actually works and know how to do microarchitecture specific optimization in high-level code. Someone who has these skills can usually squeeze out several times the performance of typical software code on more vanilla CPUs, which closes the performance gap quite a bit and for some codes the latest greatest Intel CPU will actually be faster than a hybrid architecture.
The thing to keep in mind is that most benchmark comparisons I've seen for these types of architectures are (1) narrowly selected for workloads where they excel and (2) usually compare naively optimized CPU code with expertly optimized coprocessor code. In reality, due to skill availability you often see the reverse with expertly optimized CPU code and naively optimized coprocessor code that virtually erases the apparent performance advantages.
The major hurdle for exotic coprocessor architectures is that expert code designers that know how to exploit and use these architectures are incredibly rare. Consequently, you rarely see what they can actually do. Intel's Xeon Phi coprocessor has had similar issues.