No. Actually, the state of the art of EDA software is worse.
My project has been to design (and create) better EDA software that will simulate, optimize and therefore can form and place each individual transistor optimally to achieve lower power, higher speed and lower cost.
There is only one drawback over all existing EDA software: my EDA tools must run on a ($100k) small supercomputer or FPGA cluster because it deals with a billionfold more transistors than existing EDA software and that takes more compute.
It means my software is much cheaper than existing EDA software but will yield much better chips and wafers with much faster, better, cheaper and fewer transistors.
I'm eager to give a talk on my EDA software as well, please consider inviting me to give it?
Other researchers and companies have proven that optimizing transistor design and placement over standard cell libraries and PDKs can be done, for example:
I am very certain (but have no hard proof) that this is what Apple did on their M1, M2, M3. M4 and M5 processors, especially their high end M2 and M5 Ultra chips.
What I'm claiming here is that humanity can design three to four orders of magnitude faster computer chips using at least two orders of magnitudes less energy making chips orders of magnitude cheaper if we only used better EDA software (CAD=> SYM=> FAB) that we use today. Moore's law is not at an end. I'd be happy to provide proof of this, but that takes a bit more effort than a HN comment.
I don't know about this at any detailed level, but doesn't designing standard cells for leading edge nodes involve a lot of trial and error? Is a lot of the issues that can occur even well understood to the level that it can be simulated?
With the approach you mention, would it involve creating "custom standard cells", or would the software allow placement of every transistor outside of even a standard cell grid? If the latter, I would have trouble believing it could be feasible with the order of magnitude of computing power we have available to us today.
The best results will be with custom shapes and custom individual placement of every transistor outside standard cell but within the PDK rules. Going outside the PDK rules will be even better but also harder.
The trial and error you do mostly by simulating your transistors which you than validate by making the wafers. You can simulate with mathematical models (for example in SPICE) but you should eventually try to simulate at the molecular, the atom/electron/photon and even at the quantum level, but each finer grained simulation level will take orders of magnitude more compute resources.
Chip quality is indeed limited by the magnitude of computing power and software: to design better (super)computer chips you need supercomputers.
We designed a WSI (wafer scale integration) with a million core processors and terabytes of SRAM on a wafer with 45 trillion transistors that we won't chip into chips. It would cost roughly $20K in mass production and would be the fastest cheapest desktop supercomputer to run my EDA software on so you could design even better transistors for the next step.
We also designed a $800 WSI 180nm version with 16000 cores with the same transitors as the Pentium chip in the RightTo article.
Has this WSI chip been taped out/verified? I must admit I am somewhat skeptical of TBs of SRAM, even at wafer scale integration. What would the power efficiency/cooling look like?
The full WSI with 10 billion transistors at 180nm has not been taped out yet, I need $100K investment for that. This has 16K processors and a few megabyte SRAM.
I taped out 9 mm2 test chips to test transistors, the processors, programmable Morphle Logic and interconnects.
The ultra-low power 3nm WSI with trillions of transistors anda Terabyte SRAM will draw a megaWatt and would melt the transistors. So we need to simulate the transitors better and lower to power to 2 to 3 terawatt.
There is a youtube video of a teardown of the Cerebras WSI cooling system where they mention the cooling and power numbers. They also mention that they also modeled their WSI on their own supercomputer, their previous WSI.
This sounds exciting but the enormous and confusing breadth of what your bio says you are working on, and the odd unit errors (lowering "a megawatt" to "2 to 3 terawatt), is really harming you credibility here. Do you have a link to a well-explained example of what you've achieved so far?
Are you concerned that going away from standard cells will cause parametric variation, which reduces the value proposition? Have you tested your approach on leading FinFET nodes?
Hello, I am interested in your research as well as MicroMagics. The Claremont (32nm Pentium) and MicroMagic are the only application processors that have utilized NTV by stabilizing the voltage at 350mV-500mV. I started a project to make solar powerable mobile devices https://hackaday.io/project/177716-the-open-source-autarkic-... My email is available in the github's linked.
We've designed $0,10 ultra low power 8/16/32/64 bit processor SoC with built in MPPT buck/boost converters so they can be powered directly from single solar cells or small charge Li-ion cells. They have low power networking so you can create clusters. I'm not sure yet if they will be even lower power than you 5 mW processors but 1 mW is our aim.
I would argue that a solar powered computer would benefit from a 2 megabyte (could be as low as 128KB) SRAM operating system with GUI like Squeak or Smalltalk-80 instead of a Linux as you propose. We've learned a lot from the low power OLPC designs.
Thanks for the invite, I'm eager to collaborate on your solar powered computers but I'm having trouble finding your email in your githubs. Could you email us morphle73 at g mail dot com?
That sounds very suitable for solar powered IoT and IIoT sensors, so the talk about GUI's feels confusing.
Zephyr or freertos are perfectly fine with sub-2meg amounts if SRAM.
this is pretty exciting! i agree about the squeak-like approach. what would you use for the screen? i've been thinking that sharp's memory-in-pixel displays are the best option, but my power budget for the zorzpad is a milliwatt including screen, flash, and keyboard, not just the soc
There are ultra low power ePaper displays that only need power to change pixels but need no power to light the display or hold an image. They are usually black and white or grayscale.
> Typically, the energy required for a full switch on an E-Ink display is about 7 to 8mJ/cm2.
>The most common eInk screen takes 750 - 1800 mW during an active update
The Smalltalk-80 Alto, the Lisa and the 128K Mac had full window GUIs in black and white and desk top publishing.
The One Laptop Per Child (OLPC) had low power LCD color screens especially made for use in sunlight and would combine nicely with solar panels.
hey, i've been looking for those numbers for years! where did you get them?
the particular memory lcd i have is 35mm × 58mm, which is 20cm², so at 7½ millijoules per square cm, updating the same area of epaper would require 150 millijoules to update if it were epaper. the lcd in fact requires 50 microwatts to maintain the display. so, if it updates more than once every 50 minutes, it will use less power than the epaper display, by your numbers. (my previous estimate was 20 minutes, based on much less precise numbers.) at one frame per second it would use about a thousand times less power than epaper
so in this context epaper is ultra high power rather than ultra low power. and the olpc pixel qi lcds, excellent as they are, are even more power-hungry
pixel qi and epaper both have the advantage over the memory lcd that they support grayscale (and pixel qi supports color when the backlight is on)
>At IDF last year Intel's Justin Rattner demonstrated a 32nm test chip based on Intel's original Pentium architecture that could operate near its threshold voltage. The power consumption of the test chip was so low that the demo was powered by a small solar panel. A transistor's threshold voltage is the minimum voltage applied to the gate for current to flow. The logical on state is typically mapped to a voltage much higher than the threshold voltage to ensure reliable and predictable operation. The non-linear relationship between power and voltage makes operating at lower voltages, especially those near the threshold very interesting.
I'd love to but what do you want me to elaborate on?
We started making EDA tools and simulators (CAD, SYM FAB as Alan Kay says) and designing a wafer scale integration to run parallel Squeak Smalltalk (David Ungar's ROARVM) in 2007 and we are still working on it in 2024 so I estimate 30,000 hours now. I call that very ambitious too.
>Also, have you checked out the OpenROAD[1] project? It’s a pretty impressive
No it is not pretty impressive EDA software, OpenROAD software quality is like Linux, " a budget of bad ideas" as Alan Kay typifies it. Openroad is decades old sequential program code, millions of lines of ancient C, C++ and bits of Python programs written in the very low level C language, riddled with bugs and pathes. The tools are bolted together with primitive scripts and very finicky configurations and parametric rules. Not that the commercial proprietary EDA software is any better, that usually is even worse but because you don't see the source code you can't see the underlying mess.
Good EDA tools should be written by just a few expert programmers and scientists in just a few thousand lines of code and run on a supercomputer.
So the first ambitous goal is to learn how to write better software (than the current dozens of millions of lines of EDA software code). Alan Kay explains how [1-3]:
I watched the video of your talk and it seems impressive. I work in an IP design firm, though I don't have any decision power there I could get you a foot in the door. If you're interested in trying to convince the brass, could you send an email to Eli dot senn at dolphin dot fr?
If you have working software that gives orders of magnitude improvements, needing $100k worth of hardware would be no barrier at all. That's a fraction of just the EDA software license budget for many projects.
I wouldn't want to do that, GPU compilers are not open source and the hardware is undocumented. As a scientist I feel they are extremely badly designed.
My transistor and atomic simulation software is extremely parallel but not in the limited SIMD way that GPU's are.
My project has been to design (and create) better EDA software that will simulate, optimize and therefore can form and place each individual transistor optimally to achieve lower power, higher speed and lower cost. There is only one drawback over all existing EDA software: my EDA tools must run on a ($100k) small supercomputer or FPGA cluster because it deals with a billionfold more transistors than existing EDA software and that takes more compute. It means my software is much cheaper than existing EDA software but will yield much better chips and wafers with much faster, better, cheaper and fewer transistors.
A high level overview of my software is mentioned indirectly in my talk https://vimeo.com/731037615
I'm eager to give a talk on my EDA software as well, please consider inviting me to give it?
Other researchers and companies have proven that optimizing transistor design and placement over standard cell libraries and PDKs can be done, for example:
https://www.micromagic.com/news/Ultra-Low-Power_PressRelease... was done with their own EDA software.
I am very certain (but have no hard proof) that this is what Apple did on their M1, M2, M3. M4 and M5 processors, especially their high end M2 and M5 Ultra chips.
What I'm claiming here is that humanity can design three to four orders of magnitude faster computer chips using at least two orders of magnitudes less energy making chips orders of magnitude cheaper if we only used better EDA software (CAD=> SYM=> FAB) that we use today. Moore's law is not at an end. I'd be happy to provide proof of this, but that takes a bit more effort than a HN comment.