Computer architects use the term 'memory wall' to refer to this latency problem.... | Hacker News

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		iamchp on Dec 12, 2022 \| parent \| context \| favorite \| on: SK Hynix Reveals DDR5 MCR DIMM, Up to DDR5-8000 Sp... Computer architects use the term 'memory wall' to refer to this latency problem. CPU microarchitectures are constantly improved to improve IPC, Die technology helps increase CPU frequency, but memory access latency is not keeping up with the CPU improvements.

NovemberWhiskey on Dec 12, 2022 [–]

Right - I think, at this point, that L1 cache latency is worse than main-memory latency on a 'per CPU clock' basis than it was in the late 1990s!

rbanffy on Dec 12, 2022 | [–]

Makes sense for a larger cache to take longer to decode an address.

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