This would benefit sequential access, but it'd either be disabled for random-acc... | Hacker News

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		iamchp on Dec 12, 2022 \| parent \| context \| favorite \| on: SK Hynix Reveals DDR5 MCR DIMM, Up to DDR5-8000 Sp... This would benefit sequential access, but it'd either be disabled for random-access or pollute the caches with unused lines. But in cases where sequential memory bandwidth is required, this is pretty cool! (But I assume Intel only, which would also be a bummer)

fhars on Dec 12, 2022 | [–]

RAM is the new tape...

rektide on Dec 12, 2022 | [–]

Somewhat ironic that we just reduced RAM channels from 64b down to 32b wide in DDR5 (but each DIMM has two channels). (newsflash if you missed it: desktop DDR5 is quad channel, but 32b, yes.)

SK Hynix: what if we increase the ram width to 64?

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