The 2nd stage uop can go 6-per or 7-per clock tick. But 1st stage (which executes in practice when the uop cache is thrashing) would still go 4-instructions per clock tick just fine.
> This is the length that Intel has to go to in order to keep the EUs fed.
Yeah. And the task described is O(n) total work and O(log(n)) depth. So... not a big difference? I'd have my doubts that the instruction-length portion of the decoder was taking up a significant amount of power.
The 2nd stage uop can go 6-per or 7-per clock tick. But 1st stage (which executes in practice when the uop cache is thrashing) would still go 4-instructions per clock tick just fine.
> This is the length that Intel has to go to in order to keep the EUs fed.
Yeah. And the task described is O(n) total work and O(log(n)) depth. So... not a big difference? I'd have my doubts that the instruction-length portion of the decoder was taking up a significant amount of power.