Back many years ago when I had to make a choice between these two I took a very practical approach. I learned both of them to a level adequate enough to implement a few small test projects and then I made my decisions.
How?
As a solo founder CEO/CTO/Electrical, Mechanical, Software and FPGA Engineer and, let's not forget, Janitor at the time there was one thing I valued far above anything else: Time.
VHDL, I found, is very verbose. Verilog not so. To me this meant having to type twice as much to say the same thing. This didn't sit well with me and that was the primary driver in deciding in favor of Verilog.
Another driver was familiarity with C. I had a need to switch contexts with some frequency. I was using C and C++ for embedded and workstation code development. As a mental exercise, switching to VHDL felt, for lack of a better word, violent. Switching between those languages and Verilog felt natural. Again, a time saver.
It also seemed far easier to find and hire a good Verilog engineer when the time came for me to let go of that title and focus on being a better Janitor. To me Verilog was the clear winner on all fronts. At the time it lacked a few constructs that were later added into the language yet I never found that to be a problem and managed to successfully design and manufacture many successful products.
The verbosity of VHDL isn't 2x it's more like 20% bigger on average and since VHDL 2008 it's pretty much the same. VHDL can be wordy but it also reads a lot easier & it looks more structured.
Verilog isn't C, it's C-ish, just different enough to make me make mistakes all the time like 'not' in verilog is '~' instead of '!', or the lack of overloading, the weird rules with signed & unsigned numbers and the implicit wire declarations etc. Verilog is full of surprises.
Do you like determinism? Have you ever tried running the same (System)Verilog design on multiple simulators? Almost every time you get different results, VHDL doesn't have this issue.
You seem to be taking this personally. What I described was my reasoning for choosing Verilog. It worked fine for me. I am not going to debate minutiae.
Also, who said Verilog is C? It feels like C but it isn't. It's simply a lot easier to context switch between C and Verilog than between C and VHDL. That's my opinion. You don't have to agree with it. There is no implicit obligation to agree with anything at all.
I have shipped millions of dollars in product very successfully using Verilog. Others have done so using VHDL. In the end it is a choice.
My intent was to give the OP one criteria he or she might be able to use in some way in making a similar choice.
For many years now I have been using mainly Altera and VHDL. Lately I started a new job and returned to Xilinx which I have not used for long. Part of my job is integrating three major IPs, and guess what? One of them is VHDL and two others are Verilog. So yes, sure, you can wrap a Verilog code with VHDL and forget it... but, the Verilog IPs come also with their Verilog testbenches, etc. So for me it will be a bilingual reality for some time to come.
And, please, it isn't code it is a Hardware Description Language. We all use "code" for short but let's not lose sight of what it is.
Many people come to FPGA design treating the thing as software. It isn't software. It's a hardware design and it is a hardware description language. Maybe it helps that my work in electrical engineering predates FPGA's and even PAL/PLA's. In other words, I spent years designing "raw" electronics.
When typing Verilog I think about circuits not software and I don't make a lot of mistakes because the circuits are designed on paper before typing code. Code is the hardware description, not the design environment.
I find that older hardware engineers are far better at this. Younger engineers treat it like software and go into this crazy type->debug->type->debug cycle that simply isn't the way you design hardware. Decades ago you had to know your shit. You couldn't throw a bunch of chips at a board and have to redesign it due to simple mistakes. Again, it ain't software.
So, no, I have no issues with Verilog debugging. I can't remember any serious debugging events in, say, twenty years.
What you are describing is just one aspect of programming with HDL that sounds similar to what one would do with a schematic editor. Fortunately, with HDL you can work at either a primitive level, or a more abstract behavioral level or anywhere in between. What if someone wants to design a library without knowing the specific device that will be targeted? You could use behavioral algorithmic style code using parameterized functions and lots of generate statements that could support multiple architectures. In that case there would be a lot of 'code' that does not have anything to do with the actual circuit but is still perfectly valid HDL. It is the software-like functionality of HDL that made schematic editors obsolete in my opinion.
How?
As a solo founder CEO/CTO/Electrical, Mechanical, Software and FPGA Engineer and, let's not forget, Janitor at the time there was one thing I valued far above anything else: Time.
VHDL, I found, is very verbose. Verilog not so. To me this meant having to type twice as much to say the same thing. This didn't sit well with me and that was the primary driver in deciding in favor of Verilog.
Another driver was familiarity with C. I had a need to switch contexts with some frequency. I was using C and C++ for embedded and workstation code development. As a mental exercise, switching to VHDL felt, for lack of a better word, violent. Switching between those languages and Verilog felt natural. Again, a time saver.
It also seemed far easier to find and hire a good Verilog engineer when the time came for me to let go of that title and focus on being a better Janitor. To me Verilog was the clear winner on all fronts. At the time it lacked a few constructs that were later added into the language yet I never found that to be a problem and managed to successfully design and manufacture many successful products.